64 Years of
Excellence

Information Technology

Name : Dr. Pradip Kumar Sahu
Designation : Associate Professor
Phone No. : +91-9437141295
Email Id : pksahu_it@vssut.ac.in
Date of Joining : 21-12-2016

B. E. Comp Sc. & Engineering, VSSUT, Burla (Formerly UCE, Burla), M. E. Computer Sc. & Engineering (Jadavpur University), Ph. D (IIT Kharagpur)

Embedded Systems, VLSI, NoC, SoC, Computer Architecture, Microprocessor

  1. Associate Professor, CSE & IT, VSSUT, Burla – Since 21.12.2016 to till date
  2. Assistant Professor, CSE/CSA, CET, Bhubaneswar – From 16.01.2006 to 20.12.2016
  3. Lecturer, CSE, KIIT University, Bhubaneswar – From 02.09.2003 to 15.01.2006
  4. Lecturer, CSE, UCE, Burla – From 01.07.2000 to 02.07.2001

Graduate Level :
  1. Embedded Systems
  2. Computer Organization & Architecture
  3. Advanced Computer Architecture
  4. Microprocessor and ALP
  5. Digital Logic Design
Post Graduate Level :
  1. Advanced Computer Architecture
  2.  Architecture & Operating System
  3. Networks and Distributed Systems
  4. Embedded Systems
  5. Parallel and Distributed Systems

Embedded Systems, VLSI, Network-on-Chip, System-on-Chip, Optimization Techniques, Evolutionary Computations, Cloud Computing etc.

Ph. D. Candidates : 02 Nos. (Continuing till date)
M. Tech. Candidates : 07 Nos. (Awarded)
  1. National Scholarship during B.E. at UCE, Burla
  2. National Scholarship during Diploma at BOSE, Cuttack
  3. Junior National Scholarship
  4. National Rural Talent Search Scholarship (NRTS) - Balasore District
  5. Upper Primary Merit Scholarship
  6. Lower Primary Merit Scholarship
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International Publications

  1. P. K. Sahu, and S. Chattopadyay, “A Survey on Application Mapping Strategies for Network-on-Chip Design,” Journal of System Architecture, Elsevier (JSA), vol. 59, issue 1, pp. 60-76, Jan. 2013, DOI: 10.1016/j.sysarc.2012.10.004, ISSN: 1383-7621.
  2. P. K. Sahu, T. Shah, K. Manna, and S. Chattopadyay, “Application Mapping onto Mesh based Network-on-Chip using Discrete Particle Swarm Optimization,” IEEE Transactions on VLSI Systems (T-VLSI), 22 (2), pp. 300-312, Mar. 2013, DOI: 10.1109/ TVLSI.2013.2240708, ISSN: 1063-8210.
  3. P. K. Sahu, K. Manna, N. Shah, and S. Chattopadyay, “Extending Kernighan–Lin partitioning heuristic for application mapping onto Network-on-Chip,” Journal of System Architecture (JSA), Elsevier, vol. 60, pp. 562-578, May 2014. DOI: 10.1016/j.sysarc.2014.04.004, ISSN: 1383-7621.
  4. P. K. Sahu, K. Manna, T. Shah, and S. Chattopadyay, “Thermal Uniformity-Aware Application Mapping for Network-on-Chip Design,” International Journal of Computer Applications, vol. 99 (2), pp. 8-22, Aug. 2014. DOI: 10.5120/17351-7838, ISSN: 0975 – 8887.
  5. P. K. Sahu, K. Manna, and S. Chattopadyay, “Application Mapping onto Butterfly-Fat-Tree based Network-on-Chip using Discrete Particle Swarm Optimization,” International Journal of Computer Applications, vol. 115 (2), pp. 13-22, April. 2015, DOI: 10.5120/20258-2643, ISSN: 0975 – 8887.
  6. P. K. Sahu, K. Manna, T. Shah, and S. Chattopadyay, “A Constructive Heuristic for Application Mapping onto Mesh based Network-on-Chip,” Journal of Circuits, Systems, and Computers, World Scientific, vol. 24, issue. 8, pp. 1-29, Jun. 2015, DOI: 10.1142/S0218126615501261, ISSN: 0218-1266.

Conferences

  1. P. K. Sahu, N. Shah, K. Manna, and S. Chattopadhyay, “A New Application Mapping Algorithm for Mesh based Network-on-Chip Design,” IEEE International Conference (INDICON), pp. 1-4, Dec. 2010, DOI: 10.1109/INDCON.2010.5712700, ISBN: 978-1-4244-9072-1.
  2. P. K. Sahu, N. Shah, K. Manna, and S. Chattopadhyay, “An Application Mapping Technique for Butterfly-Fat-Tree Network-on-Chip,” IEEE International Conference on Emerging Applications and Information Technology (EAIT), pp. 383-386, Feb. 2011, DOI: 10.1109/EAIT.2011.37, ISBN: 978-1-4244-9683-9.
  3. P. K. Sahu, N. Shah, K. Manna, and S. Chattopadhyay, “A New Application Mapping Strategy for Mesh-of-Tree based Network-on-Chip,” IEEE International Conference on Emerging Trends in Electrical and Computer Technology (ICETECT), pp. 518-523, Mar. 2011, DOI: 10.1109/ICETECT.2011.5760170, ISBN: 978-1-4244-7923-8.
  4. P. K. Sahu, P. Venkatesh, S. Gollapalli, and S. Chattopadhyay, “Application Mapping onto Mesh Structured Network-on-Chip using Particle Swarm Optimization,” IEEE International symposium on VLSI (ISVLSI), pp. 335-336, July 2011, DOI: 10.1109/ISVLSI.2011.21, ISBN: 978-1-4577-0803-9.
  5. P. K. Sahu, A. Sharma, and S. Chattopadhyay, “Application Mapping onto Mesh-of-Tree based Network-on-Chip using Discrete Particle Swarm Optimization,” IEEE International Symposium on Electronic System Design (ISED), pp. 172-176, Dec. 2012, DOI: 10.1109/ISED.2012.17, ISBN: 978-1-4673-4704-4.
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  • REVIEWER  
    • IEEE Canadian Journal of Electrical and Computer Engineering
    • IET Computers and Digital Techniques
    • Journal of Systems Architecture, Elsevier
    • Inderscience_International Journal of Information and
    • Communication   Technology (IJICT)
  • MISCELLANEOUS
    • Winner of Computer quiz at UCE, Burla in the year of 1998.
    • Winner of best Literian at UCE, Burla in the year of 1999.
    • Winner of 1st position in Creative Writing at UCE, Burla in the year of 1999.
    • Winner of 1st position in Debate at UCE, Burla in the year of 1999.
    • Editor of College Magazine “LIPSA” at UCE, Burla in the year of 1999.
    • Organizing member of the Conference ICWA at CET, Bhubaneswar from 18th to 21st December, 2013.
Present Address : 
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